The present invention generally relates to fabrication of semiconductor devices and more particularly to a method for fabricating a semiconductor device wherein a bipolar transistor and a metal-insulator-semiconductor (MIS) transistor are provided on a same substrate.
With the demand for high speed semiconductor devices having a large integration density, semiconductor devices including bipolar transistors with the self-aligned emitter-base structure and metal-oxide-semiconductor (MOS) transistors on a same substrate are marketed. Such semiconductor devices provide a preferable feature as a result of combination of the characteristically small parasitic capacitance of the bipolar transistors and the characteristically low power consumption of the MOS transistors.
When fabricating such a semiconductor device wherein semiconductor devices of different type are provided on a same substrate, fabrication of the semiconductor device of each type is made concurrently so as to improve the efficiency of production. In such a process of fabrication, it is desired to form the surface of the semiconductor device flat so that the formation of steps, which may cause the disconnection of interconnection conductor patterns provided on the surface of the semiconductor device, is suppressed or eliminated.
FIGS. 1A-1J show the fabrication steps of a conventional semiconductor device of the foregoing type.
Referring to FIG. 1J showing the completed semiconductor device at first, the semiconductor device comprises a silicon substrate 1 of the p-type, an epitaxial layer 3 of the n-type silicon grown on the substrate 1, a pair of buried layers 2a and 2b of the n.sup.+ -type formed at a boundary between the substrate 1 and the epitaxial layer 3 respectively in correspondence to a MOS transistor and a bipolar transistor formed commonly on the substrate 1, the buried layer 2b thereby acting as the buried collector of the bipolar transistor, an n.sup.+ -type emitter region 10 formed in correspondence to the surface of the epitaxial layer 3 as the emitter of the bipolar transistor, a base region 7 of the p.sup.- -type formed in the epitaxial layer 3 underneath the emitter region 10 as the base of the bipolar transistor, an outer base region 7a of the p.sup.+ -type formed in the epitaxial layer 3 so as to surround the inner base region 7 laterally, a diffusion region 8a of the p.sup.+ -type formed in the epitaxial layer 3 as the source region of the MOS transistor, a diffusion region 8b of the p.sup.+ -type formed in the epitaxial layer 3 as the drain region of the MOS transistor, an insulator film 4 provided on the top surface of the epitaxial layer 3 in correspondence to the MOS transistor as the gate insulation film, an isolation region 4a of an insulator material same as the material forming the insulator film 4 for isolating the MOS transistor and the bipolar transistor from each other, a collector contact region 5 formed in the epitaxial layer 3 in correspondence to the bipolar transistor so as to extend from the surface of the layer 3 to the buried layer 2b, a polysilicon gate electrode 6a provided on the insulator film 4 as the gate of the MOS transistor, a polysilicon base electrode 6b provided on the epitaxial layer 3 in contact with the outer base region 7a, and a polysilicon emitter electrode 6c provided in contact with the emitter region 10 and separated from the base electrode 6b by a second insulator film 4b.
Next, the problems of the conventional semiconductor device addressed by the present invention will be explained with reference to the fabrication process shown in FIGS. 1A-1J.
In a step of FIG. 1A, the insulator film 4 of silicon oxide is grown on the silicon epitaxial layer 3 which is provided on the silicon substrate 1 with the buried layers 2a and 2b formed between the substrate 1 and the epitaxial layer 3. The insulator film 4 may be a layer of silicon oxide formed by the thermal oxidation process.
In a step of FIG. 1B, an ion implantation is made through the insulator film 4 in correspondence to where the collector contact region is to be formed and after an annealing process performed subsequent to the ion implantation, the collector contact region 5 of the n.sup.+ -type is formed as illustrated.
In a step of FIG. 1C, the device isolation structure 4a is formed by applying an oxidation process selectively so as to separate the region of the epitaxial layer 3 on which the MOS transistor is to be formed from the region on which the bipolar transistor is to be formed. It should be noted that the region of the epitaxial layer 3 where the collector contact region 5 is formed is covered by the thin insulator film 4.
In a step of FIG. 1D, a first polysilicon layer 6 is deposited uniformly on the insulator layer 4 including the isolation structure 4a as illustrated, and the second insulator film 4b is formed on the polysilicon layer 6 in a next step of FIG. 1E. Further, an ion implantation process is performed in the step of FIG. 1E wherein the p.sup.+ -type outer base region 7a of the bipolar transistor is formed.
In a step of FIG. 1F, the first polysilicon layer 6 as well as the second insulator film 4b are patterned and thereby the gate electrode 6a and the base electrode 6b are formed. Further, a contact hole 13 is formed through the base electrode 6b, and the exposed side surfaces of the gate electrode 6b and the contact hole 13 are oxidized. As a result, the second insulator film 4b at the top of the gate electrode 6a is connected to the first insulator film by the oxide film formed at the side walls of the gate electrode 6b. At the same time, the surface of the epitaxial layer 3 exposed at the bottom of the contact hole 13 is covered by an oxide film.
In a step of FIG. 1G, the thickness of the insulator films 4 and 4b including the side wall of the gate electrode 6a and the contact hole 13 of the structure of FIG. 1F is increased by growing the insulator film further and the insulator film 4b covering the top surface of the gate electrode 6a and the base electrode 6b as well as the insulator film 4 covering the epitaxial layer 3 is selectively etched by applying an anisotropic etching process acting vertically to the major surface of the epitaxial layer 3. Thereby, the a thick oxide is remained at the side surface of the gate electrode 6a and at the side wall of the contact hole 13. Next, an ion implantation process is carried out to the epitaxial layer 3 at both sides of the gate electrode 6a, and thereby the source region 8a and the drain region 8b are formed as illustrated. As the same time, the ion implantation is made also through the contact hole 13 and thereby the inner base region 7 is formed in the epitaxial layer 3.
In a step of FIG. 1H, the thickness of the oxide at the side surface of the gate electrode 6a and at the side wall of the contact hole 13 is increased by growing the insulator film on the structure of FIG. 1G and by applying the anisotropic etching as already described with reference to the step of FIG. 1G. Thereby, the diameter of the contact hole 13 is reduced. Further, the insulator film is removed from the bottom of the contact hole 13 and also from the part of the epitaxial layer 3 wherein the collector contact 5 is formed. Further, a second polysilicon layer 6.sub.1 is deposited on the entire surface of the structure thus formed, and implantation of impurities is made into the layer 6.sub.1. The impurity elements thus introduced are diffused into the epitaxial layer 3 immediately in contact with the electrode 6c in the subsequent heat treatment.
In a step of FIG. 1I, the second polysilicon layer 6.sub.1 is patterned to form the electrode 6c for the emitter and the electrode 6d for the collector of the bipolar transistor. Further, a CVD process is carried out such that the the entire surface of the structure thus formed is covered by the oxide film forming the second insulator film 4b. As a result of the heat treatment which is accompanied with the CVD process, the impurity elements in the electrode 6c are diffused into the epitaxial layer 3 immediately in contact with the electrode 6c and the emitter region 10 is formed in the surface part of the base region 7.
Next, a liquid insulator material commonly known as spin-on-glass (SOG) is applied on the oxide film by a spin coating process. Thereby, any depression formed on the structure is filled by an SOG layer 12 as shown in FIG. 1I, and the unwanted steps on the surface of the device which tend to cause the disconnection of the interconnection conductors are smoothed. After the layer 12 is applied, the layer 12 is cured by a heat treatment process which is carried out at a relatively low temperature typically of about 800.degree. C. When the layer 12 is applied, the SOG has a low viscosity and a planarized surface suitable for providing interconnection thereon is obtained at the top surface of the semiconductor device.
After the layer 12 is cured, contact holes are provided in correspondence to the source, gate and drain of the MOS transistor and in correspondence to the collector, emitter and base of the bipolar transistor. Further, an interconnection conductor is deposited and patterned in correspondence to the contact holes. Thereby, the completed device structure having interconnection electrodes 11a-11e is obtained as shown in FIG. 1J.
According to the present structure, the risk that the interconnection conductors on the top surface of the device connecting the electrodes 11a-11e is damaged is significantly reduced by the planarized top surface, and the improved yield as well as the reliability of the semiconductor device are expected.
Alternatively, the semiconductor device may be covered by a phosphosilicate glass (PSG) layer 9 as shown in FIG. 1K. In this case, the PSG layer 9 is deposited on the second insulator film 4b after the step of forming the emitter and collector electrodes 6c and 6d are formed and the oxide layer grown on the electrodes 6c and 6d. This PSG layer 9 is heat treated subsequently at a temperature of typically 1100.degree. C. to cause reflowing, and thereby a planarized surface is obtained at the top surface of the semiconductor device as shown in FIG. 1K. Further, the contact holes are formed in correspondence to the source and drain electrodes of the MOS transistor and in correspondence to the collector, emitter and base of the bipolar transistor, and the electrodes 11a-11e are provided in correspondence to the foregoing contact holes as shown in FIG. 1L. In this structure, too, the top surface of the semiconductor device is planarized and the improved yield and reliability of the device are expected.
In the foregoing process, particularly the one using the SOG for planarization of the device explained with reference to FIGS. 1A-1J, there arises a problem in that the second insulator film 4b may be etched excessively when forming the contact hole for the electrode 11d for the emitter region 10 of the bipolar transistor. More specifically, there appears a deep depression in the second insulator film 4b in conformance with the shape of the contact hole 13 as shown in FIG. 1I when the layer 4b is grown, and this depression is inevitably filled by the SOG which is shown in FIG. 1I by a reference numeral 12a. When providing the electrode 11d in contact with the emitter electrode 6c which is buried under the insulator film 4b which in turn is buried under the SOG 12a filling the depression, a deep etching is needed in order to remove the thick SOG layer 12a and expose the top surface of the emitter electrode 6c. When the ething is applied to form such a deep contact hole, there arises a risk that the polysilicon base electrode 6b is exposed by the contact hole and makes a contact with the electrode 11a as shown in FIG. 1J. Further, such an etching, used to form the contact hole for the electrode 11d, is used simultaneously to form the contact holes for the interconnection electrodes 11a and 11b for the source and drain of the MOS transistor. As the insulator film 4 covering the source region 8a or drain region 8b of the MOS transistor is thin even considering the thickness of the SOG layer 12 thereon, there is a substantial risk that the source and drain regions 8a and 8b are etched excessively as illustrated in FIG. 1J and the characteristic of the device is significantly deteriorated. Further, the use of thin insulator layer 4 raises a problem in that the insulator film may be easily damaged in response to the current flowing through the electrode 11a or 11b. When this occurs, the reliability of the semiconductor device is seriously deteriorated.
In the case of the process including the steps of FIGS. 1K and 1L wherein the reflowing of PSG is used, on the other hand, there arises another problem in that the emitter region 10, formed as a result of diffusion of impurity elements from the emitter electrode 6c into the base region 7, may grow excessively and reach the collector region 3 of the bipolar transistor underneath the base region 7. Such an excessive diffusion may occur due to the relatively high temperature of heat treatment needed for the reflowing of PSG. A similar problem occurs also in the MOS transistor such that the source region 8a and the drain region 8b are grown excessively by the diffusion of the impurity elements in response to the heat treatment and may become continuous particularly when the gate length is reduced. Such excessive growth of the diffusion region is detrimental to the operation of the MOS transistor as well as bipolar transistor. In order to avoid these problems, the conventional semiconductors have to be designed to have a relatively large gate length and a relatively large base thickness. However, increase in the gate length and increase in the base thickness both contribute to the decrease of the operational speed of the transistors. Thus, the semiconductor devices produced in accordance with the foregoing process had the problem of unsatisfactory operational speed in addition to the problem of poor reliability.
From the view point of achieving an excellent operational speed for the bipolar and the MOS transistors, it is essential to use the SOG at the time of planarization and prevent the excessive diffusion of impurities such that the gate length and the base thickness are reduced. Therefore, a process of fabricating the device wherein the foregoing problems are eliminated while still allowing for the use of the SOG for the planarization of the device is strongly demanded.